The present invention relates generally to integrated circuit layout, and more specifically to verification of integrated circuit layouts.
Typical micron level integrated circuit manufacture requires extensive layout of components and pathways between components. The pathways between components carry signals and power back and forth between components. Some components do not require much power or do not carry much current. Pathways between these types of components can be made very small in width of the metal that carries the signals or the power. However, other components have higher power or current requirements.
As power and current requirements go up, a standard minimum line width for carrying power or current between or to those components is insufficient. Typical minimum line widths for components that do not draw much current are on the order of 0.2 microns wide. On the other hand, lines that carry power or current to or from supplies and large components may need to be on the order of 10 to 1000 microns wide. The wider lines are required to carry the current as well as to avoid resistive drops and electro migration problems.
Various software solutions exist to perform certain checking of parameters in schematics, layouts, and the like. A typical design process begins with schematic, moves to layout, and then to design and on to fabrication. Along the way, checks are typically made of parameters and the like. For example, a line width check program checks to see if the lines in the (schematic or layout) are at least at or above an absolute minimum width (usually 0.2 microns). When the layout is complete, aside from the line width check, an inspection is made, typically manually, of checking that the lines that are required or called for to be a width greater than the absolute minimum are indeed laid out at the required or called for widths. Since integrated circuits can be extremely complex, such a visual inspection is very time consuming, and is prone to human error.
Once the layout is complete, a layout versus schematic program is run. The layout versus schematic program compares the electrical circuit design (schematic) with the physical design (layout). Once the layout is complete and checked with the LVS, a design is extracted. When the design has been extracted, a design rule checker (DRC) program is run. The DRC measures spacing, overlap, and sizes of masking dimensions and the like on the layout to ensure that circuit dimensions will conform to the fabrication process capabilities. The DRC includes a check for line widths only to the extent that it checks to see that each line is at least an absolute minimum width. Lines requiring a greater width are not verified to that greater width.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved checking of layout line widths in integrated circuit layouts.
In one embodiment, a method for checking accuracy of an integrated circuit includes tagging at least one line with a width marker, laying out the lines, retrieving the width marker for each tagged line, and comparing the actual line width with the marker line width.
In another embodiment, a method of checking for errors in line width in an integrated circuit includes defining a line width layer, identifying with a marker any lines having a line width greater than a default minimum line width, and associating a line width parameter with each line width marker, the line width parameter corresponding to a line width for the marked line. The line width parameters and line width markers are converted to lines in a layout, and the line width parameters for each line width marker are compared to the actual layout line width.
In yet another embodiment, a method for checking layout accuracy in an integrated circuit design includes creating a schematic, adding a line width marker to selected lines having a width greater than an absolute minimum width, and assigning a line width to each line width marker. A layout is created from the schematic, and the layout is checked versus the schematic. A design is extracted from the layout, and the design line width marker is checked versus the marker line width for each line having a line width marker.
In still another embodiment, a method of performing a design rule check on an integrated circuit includes tagging at least one line with a width marker in a schematic, extracting each line having a width marker in a layout, comparing the schematic versus the layout, checking a layout line with the extracted width, and generating an error condition for any line with a layout width less than its extracted width.
In yet another embodiment, a method of performing a layout versus schematic check on an integrated circuit includes comparing layout line widths with existing line width marker parameters for selected lines of the circuit, and indicating an error if a layout line width is less than its line width marker parameter.
In another embodiment, a method of identifying line width errors in an integrated circuit design includes adding a line width marker for each of a plurality of lines on a schematic, assigning a line width parameter to each line width marker, creating a layout from the schematic, the layout containing the line width markers, checking the layout line widths versus the schematic line widths for the plurality of line width marked lines; creating a design from the layout, and checking the design line widths versus the layout line widths for the plurality of line width marked lines.
In still another embodiment, a method of design rule checking an integrated circuit includes identifying any line having a line width marker and line width parameter, extracting each line having a line width marker, determining the line width parameter for each extracted line, and comparing the line width parameter with an actual line width for the line.
In still another embodiment, method of design rule checking an integrated circuit includes identifying any line having a line width marker and line width parameter, excluding the line if it is near or above a transistor, extracting each line having a line width marker, determining the line width parameter for each extracted line, and comparing the line width parameter with an actual line width for the line.
In another embodiment, a schematic for an integrated circuit includes a number of circuit components interconnected by lines, a number of width markers each assigned a width marker having a minimum width parameter.
In another embodiment, a schematic for an integrated circuit includes a number of circuit components interconnected by lines, and a line width layer including a line width marker for each line having a width greater than a standard minimum width, and a line width parameter for each line width marker.
Other embodiments are described and claimed.